Experiments with JFET Biasing

The most common way of biasing a Junction Field Effect Transistor (JFET) is with a source resistor. This method, shown in Fig 1 below, has the advantage of offering negative feedback to stabilize the bias conditions. This is the same thing that happens when a bipolar transistor uses an emitter resistor. Self bias can be used as a method to evaluate a JFET to determine the critical parameters that describe it: Idss and Vp. These are discussed in Chapter 2 of Experimental Methods in RF Design and many other places.

The method used in our experiment is to set up the FET of interest in a test fixture with a power supply, bypass capacitor, resistors in the drain and gate to suppress parasitic oscillations, and a handful of extra resistors, R-test, that can be paralleled with an existing 100K source resistor. A digital volt meter (DVM) is the basis for the measurements. We begin by using the DVM to measure the resistance of our test resistors, for the values will be used in calculations. The DVM is then attached to the FET source to measure the DC voltage. The first value we measure is with no attached R-test. The measured value will be very close to the FET pinchoff voltage.

The measurements we will perform infer drain current as a function of gate ‑to‑source voltage. The physics of the FET support the model that there is no gate current so long as the gate is not forward biased with regard to the source. Hence, the drain current equals that in the source. We will measure the source current by measuring the voltage drop across the source resistor. The gate is at ground potential, for there is no gate current, so the gate‑to‑ source voltage is just the negative of the source to ground voltage.

The resistors that I pulled from my stock for some measurements were marked as 22, 39, 68, 100, 150, 300, 510, 680, 1K, 2K, 3.3K, 6.8K, and 10K Ohm. The measured values are shown in attached figures. A systematic pattern was noticed with all of the measured resistances under the marked value, suggesting an error in the calibration of my DVM, a Fluke Model 73. All resistors were 2% carbon film 0.25 Watt. However, when I measured a 499 Ohm, 1% metal film resistor, it came up exactly at 500 Ohms. The differences between the measured values and those marked on the part were small enough that I neglected the details and used measured values for calculations.

The first FET I examined was a 2N5454, a common JFET that I had in my junk box. The source voltage was 3.26 with nothing but the 100K for source bias. I started my measurements with the largest resistor, 10K. The voltage dropped to 2.90 and was stable. I merely held the resistor in place rather than soldering it. The resistor was kept in place long enough to get a stable reading that I could record in my lab notebook. All results were of the same character until I got to the 300 Ohm resistor. At that point I started to notice a slight heating effect. The source voltage was 1.523, but slowly dropped to 1.518 volts. This behavior continued through the lower value resistors. The 22 Ohms produced 264 mV on the source that then dropped to 256 mV.

Later I examined a J310 JFET. This is a much larger area part than the 2N5454 with an Idss that is about three times larger. With the 22 Ohms in the test fixture, V-source went to 701 mV, but settled at 652 mV. The drain current was then 32 mA. With a 10 volt power supply, there was nearly 200 mW dissipated in the FET. This is within ratings, but high enough to produce heating. Operation at higher voltages and at Idss would further tax the part. One must take care when doing these measurements to be sure that the source voltage is observed quickly.

Attached are the MathCad documents that I used to examine the data. A spread sheet such as Excel could be used, but I prefer the graphics of MathCad. The second page for the 2N5454 shows a graph for the observed data as well as a calculated one. The two FET parameters for the 2N5454 were varied to obtain a good correspondence between the two. The part had Idss=15 mA with Vp=-3.5 volts. This is similar to the popular MPF-102, but close to the high Idss extreme for that part.

The data presented for the J310 is more abbreviated with only two points shown. I picked the 22 Ohm and 1K source resistors. This still produced data that is very close to that obtained with many more data points.

My initial analysis suggested that we could characterize the FET by measuring the source voltage with 100K in place to approximately determine Vp, and to then short circuit the source through the mA scale on the DVM to obtain Idss. This is a reasonable start. However, the pinchoff will usually be a few percent more negative (for an N-channel depletion mode part). The long leads in the source also make me feel uncomfortable with regard to parasitic oscillations.

After the DC measurements were done, I thought it wise to look at the potential for oscillation. The J310 was in the test circuit at this time. The TO-92 J310s are parts that are well known for their propensity for oscillation, so I guessed that it would not be difficult to coax this one into such a mode. But this was not what I found. I eliminated the 100 Ohm drain resistor, but moved the FET close to the 0.1 uF bypass. This bypass is not a very good one for VHF and upward. No oscillation was seen. I then eliminated the gate resistor, replacing it with the normal gate lead. Still no oscillation. I eventually added a gate inductor and a parallel tuned circuit in the source. The source bias resistor had a RF choke in series with it. I finally saw a robust VHF oscillation, but nothing else up through 1.5 GHz.

18 Feb, 2006 by W7ZOI

Many thanks to Wes, W7ZOI for this contribution.