Electronic Hobbyist Circuits 2010

This page houses a collection of brief hobbyist experiments.

1.  LM380 Power Examination

Figure 1 shows the test set up. This is a good part with an input impedance of 150kΩ. The gain is internally fixed at 34 dB. The average clean power was 508 mW.  The test input frequency was 1018 Hertz.

The breadboard of Figure 1 is shown above.

2.  Wide Range L- C Oscillator

Shown above is a single frequency version of a VFO topology which allows a wide frequency range when additional switched inductors and/or capacitors plus a tuning variable capacitor are used. One good usage example would be a to use such a VFO to drive a bridge to make a wide range antenna analyzer. Q1 is essentially a common gate amplifier. The source is driven and the output is taken off the drain. This FET exhibits no signal phase shift. Q2 is a source follower that is AC coupled through that 22 pF capacitor The 18 ohm resistor is used to kill UHF parasitic oscillations. The Q2 follower also has no phase shift. Connecting the output of Q2 back to stage Q1 gives zero phase shift. The L-C tank will select the frequency where 0 phase shift is obtained. The tank will show phases other than 0 away from its resonance.

Q3 is an AC-coupled source follower to further buffer the VFO from its load. The RFC can be anything from your junk box, although it should likely be low Q. The low-pass decoupling filter on the the 12 volt supply path can also be anything reasonable. I wound mine using 17 turns on an FT37- 43 ferrite toroid. Its purpose is to keep RF from traveling down the 12 volts DC voltage wire to other parts of your circuit.

Any component connected to the L-C tank (at the Q1 drain, or the cold end of L1) can affect VFO tuning and drift. Temperature compensation will be necessary to achieve perfect stability. I use NP0 and C0G caps interchangeably. In the design shown, stability was good and the output had low measured distortion. This VFO will pretty much oscillate with any reasonable L and C values in the tank circuit. I found frequency stability was a little better with a higher L to C ratio. This is a great experimenter's circuit. One version built oscillated at 150 MHz.

The breadboard of the above schematic. Pull the wire on your #6 powdered iron toroids tight to prevent air gaps between the toroid and the wire. Number 26 gauge wire was used on L1 as shown. High Q tank parts will garner the best results.

Some potential switching ideas are presented above. The builder is in total control of the tuning range and must calibrate the L and C values according to needs and the parts on hand. Output power will vary according to the L-C ratios and some designs include automatic signal amplitude leveling and/or RF gain controls.

3.  FET Matching

I find matching high IDSS FETs like the J310 to be a pain. I generally matched them for IDSS and occasionally for IDSS and VP. Observations that when the IDSS of 2 or more FETs match, their pinch-off voltage (VP) also matches, led me to not measure VP. In addition, the variability of VP measurements causes me distress. Click here for a tutorial if you don't understand the terms IDSS and VP.

Above — The device I use to measure IDSS and VP. From Ken Kuhn's web site.

Conceptually IDSS and VP aren't difficult to understand — measuring them is another story. With the above device, first IDSS is measured; the final drain voltage potentiometer setting is left and then I measure VP. While measuring IDSS in high IDSS FETs, heating can occur and you may actually see current start to drop as you increase the drain voltage (negative temperature coefficient). On J310 specification sheets, the manufacturers state they pulse the current during measurement to prevent heating. While performing IDSS measurements, I am fearful of destroying the FET I am trying to characterize! Measuring VP is also problematic.

I have tried 3 methods to quantify VP:

  1. Adjust the 0 - 6 volt supply until I think the current goes to 0. Serial measurements 1 day apart can vary by a variation of as much as 0.5 volts; it's quite subjective.
  2. Adjust the 0 - 6 volt supply and measure the gate voltage that produces a drain current somewhere between 0.1 and 1 percent of IDSS and declare that to be VP.
  3. Adjust the 0 - 6 volt supply so the ammeter reads IDSS and multiply this voltage by - 2.0. Refer to Ken Kuhn's site for details. Although reasonably accurate, the second order math is only a rough approximation — the real math is impossible to do by hand as it involves fractional exponents and these exponents and other factors vary as a function of the physical JFET geometry.

Above — The breadboard of the device I use to measure IDSS and VP. There is no actual switch, I either ground the green wire to the copper board, or tack solder it to the 0 - 6 volt potentiometer wiper. 10 megohm resistors plus the pot ground wire anchor each pot to the copper clad board.

All 3 methods to quantify VP frustrate me. There must be a way to match J310s or other FETs without characterizing them. I frequently collaborate with readers to problem solve and learn. A potential solution contributed by a supportive reader follows:

Above — A bridge is used to match a pair of JFETS. It's often best to match devices in a circuit that closely resembles the one that you intend to use them in. The differential output of each drain is measured by placing a DVM lead on each drain and recording the voltage. Generally, I stick a FET in the Q2 slot and put FETs from my parts bin in the Q1 slot to match it. The results of 5 different FET pairs are tabled above. A match <= 50 mV is probably acceptable and in 1 case, I found a match of 3 mV! You can match 1 FET with many using this device.

Note the poor match when an MPF102 and a J310 were tested. 1% tolerance resistors are recommended for the bridge.

Above — A set and forget precision bridge using trimmers to establish a perfect DC match on both halves. If you don't have 1% parts, the trimmer resistors offer a solution. You can place a trimmer at either the drain or source end as shown and just use 5% resistors. Calibrate each half of the bridge with your ohm meter. I cover bridges on this web page if you need more information on them.

Above — A differential FET matcher breadboard. This version had a 9.1M gate resistor on Q1 by accident, although it made no difference to the experiment, as no DC gate current flows.

4.  BJT and Diode Matching

Above — Differential BFT matcher. Differential voltage matching works for bipolar junction transistors and diodes also. PN junctions are thermally sensitive — let them stabilize before testing. I measured 6 2N3904 transistors and the tabled results remind us why this transistor isn't the best choice for matched BJT circuits.

Above — The breadboard of the differential transistor matcher. Any reasonable resistor values will work fine, but don't run the current too high — my circuit has a nominal emitter current of 2.25 mA.

Above — The differential diode matcher. The 10K pot allows you to vary the current to suit your needs. The ammeter reads double the diode current. Considering only 1 diode; the current ranges from 0.01 to 5.82 mA. You can drop the 1% metal film 2K0 resistors down as low as 470 ohms or so if you need serious current. Tabled are some measurements performed with the 10K pot dialed to give 0.636v (77.3 uA per diode). This provided excellent sensitivity. Measurement was performed on my DVMs 200 mV scale. Builders might experiment with diode current to assess measurement sensitivity and linearity or even to match the diodes across a range of current values.

Clear glass passivated diodes can be affected by light — photons will pass through the glass and knock electrons through the barrier. Ensure each D.U.T is exposed to the same amount of ambient light. Some microwave detector diodes can be damaged with as little as 1 mA of current. Replace the 2K0 resistors with 10-15K resistors, or lower VCC to prevent damage .

Above — Breadboard of the differential diode matcher. The 2K0 resistors are suspended by a vertically mounted 10M stand-off resistor.

5.  Bipolar Junction Transistor Beta Tester

Above — Disappointed with the transistor beta testers in our common, low-cost digital multimeters, we did the logical thing; designed and built our own. This collaborative project was more an experiment with BJTs than anything else. It's about as simple a beta measurement device as you can make and still get good results. Preventing damage to our parts inventory underpins this design — the 100 emitter resistor plus ~ 10 microamps of base bias keeps the IC low to help avoid smoke since most new small signal transistors have a beta of 100-400.

Ensure the correct polarity for PNP versus NPN transistors. The voltage divider targets 5 volts using a standard ~12 volt supply; I just used whatever resistors were handy and ended up with the 6K8 — 3K3 pair. VCC should be regulated. Perform the measurements with a single multimeter allowing time for stabilization.

To use: Set the potentiometer so that the voltage drop across the 10K resistor is 100 mV. Then move your DMM leads to the 100 Ω resistor and measure the beta. This device measures beta, the static gain at DC.

Measuring beta is a bit inexact since beta is affected by so many variables as follows:

  1. Beta tends to be low at low operating currents and rises and plateaus for medium currents and then falls at higher currents.
  2. Beta tends to increase with temperature.
  3. Beta is affected by the voltage between the collector and emitter -- this is a weak effect except when the voltage is very small.
  4. The beta can vary as the battery depletes in DMM beta testers.

Above — Breadboard of the QRP beta tester. We hope you have as much fun with this circuit as we did.

Above — Testing a 2N2222a. We found measuring transistors to be very instructive; comparing our results to specification sheets, handling the different BJTs, gaining experience — all part of the exciting world of bench electronics. Such circuits, although simple, are great for both learning and design.

6.  FET Tester - VGS Measurement Tool

Above — A FET VGS Tester. The final collaborative output from late December 2010: a device to examine VGS. A zener diode value from 6 -7.5 volts or so should work okay. VDS should be greater than the nominal VP for greatest accuracy. The VDS using 7.5 volt zener diode was 4.85 volts. The range of VGS on my breadboard was roughly 6 to -6 VDC without the 470K range limiting resistor; it's up to you if you want to limit the VGS range.

Using the mV scale on your DVM, potentiometer adjust the current until the meter just reads 0. Then move your leads to the VGS test points to read the pinch-off voltage.

The 0 current point will only ever be close. The interesting issue with the 0 point as defined is it never goes to true zero — just zero enough —that point may be hidden if your meter scale truncates lower current measurements to zero. If you're able to repeatedly get consistent VP measurements with whatever method your using, then it's likely accurate.

We thought about measuring gate leakage current across the 10K gate resistor, but accurate measurement is impossible with this device. The gate leakage current is going to be in the low nanoampere region at the very highest unless the JFET is bad. The expected voltage across the 10K resistor would be a few 10s of microvolts. A better way to measure gate leakage is to use the 10M resistance of a DVM instead of this resistor. The DVM then acts as a current meter by measuring the voltage across the 10M resistance. A reading of 200 mV would mean a current of 20 nA.

Above — Front view of the FET tester with a "chicken head" knob on the potentiometer.

Above — Measuring a J310 with the FET tester prototype breadboard.

Above — Instead of a zener diode, low impedance VCC/2 splitters are shown as A and B; the zener diode is easier.

Above — Reverse view. I didn't bother with the 470K VGS range limiting resistor in my breadboard.