JFET BIASING TUTORIAL BY W7ZOI
This tutorial is copyright © 2000-2001 by Wes Hayward, W7ZOI and may not be presented elsewhere.
Basic behavior of an N-Channel depletion mode JFET.
The numbers shown basically illustrate the ideas.
Circuit used to determine FET DC parameters.
Data and smooth curve for a 2N5454 we measured.
This FET has a pinch off of -2.8 volts and a IDSS of 11 mA.
Data used to produce transconductance for the FET used in our sample amplifier.
Common source amplifier biased for 5 mA drain current.
Amplifier with "long tail" biasing. This amplifier is biased for 5 mA and is identical in performance to that of Figure 5, but does not require the careful device characterization.
