Shown in Figure 1 is the base 7.0 MHz VFO used in all the experiments on this web page. The AC output voltage can be controlled by changing the value of RX. A single 1 pF silver mica capacitor in the tank circuit provided temperature compensation. It took ~1.5 hours to find the right combination of fixed capacitors to eradicate frequency drift and establish the desired tuned frequency range. The main tuning capacitor is at least 40 years old.

Shown above is a photograph of the Figure 1 breadboard.

Shown above is the Figure 1 VFO output in my oscilloscope. Scope tracings were photographed at an angle to avoid reflection of the camera in the CRT. This is a pristine sine wave. This VFO requires no low pass filtering since harmonic content is low.

Shown above in Figure 2 are the waveforms of Figure 1 driving a BJT driver/switch (A) and then a JFET driver/switch (B). You see this technique used a lot, but unfortunately only 1/2 of the sine wave is squared up. I had my oscilloscope set at X5 magnification to better visualize the resultant waveforms.

Shown above is an unmagnified look at the JFET switch (B) output waveform

Following the Figure 2 circuits, another circuit was connected to the VFO and is shown above in Figure 3. This time, a two input NAND gate Schmitt trigger configured as an inverter was tested. The first Schmitt gate is biased via a 10K pot to provide an adjustable trigger threshold. I actually forgot to write down the bias voltage where the gate snapped on, but as I recall, it was somewhere between 5 and 6 volts.

Shown above is a photo of the Figure 3 breadboard. You can see the temporary AC-coupled 51 ohm load resistor to the left. I used this load in both the Figure 2 and 3 circuits. In these experiments, I also tried other load resistor values. It was learned that different load impedance can affect the waveform shape to an extent, although not the symmetry. I also tried driving the Figure 2 and 3 circuits using a high impedance. The 3-turn link on T1 of Figure 1 was disconnected. A 10 pF C0G capacitor was then connected to the hot end of Q1 (at the junction of the 33 and 1K8 resistors) and to then to the Fig 2 and 3 inputs; however, this did not change the output waveform shape to any extent.

Shown above is the Figure 3 output. This waveform resembles those of Figure 2. While the BJT, FET and Schmitt triggered NAND gate worked okay, I wanted a symmetrical AC waveform, so further experiments were conducted.

Shown above in Figure 4 is a single-ended differential amp which gave a much better output waveform than the circuits used in Figures 2 and 3. A 10K pot was used to determine the bias voltage required to give the best looking square wave. This was ~ 6.4 volts. I then swapped the potentiometer with the 8K2/6K8 voltage divider. This was exciting; I was getting closer to a pure square wave. During testing, the load was an AC-coupled 51 ohm resistor similar to Figures 2 and 3. The waveform symmetry was marginally better when the circuit was driven with a low impedance.

Shown above in Figure 5 is an inverter which was connected to the output of the differential amp. Note that in Figure 5 that the first 4049 gate is biased at VCC/2 using a 4K7/4K7 voltage divider. It is necessary to do this because the maximum AC voltage of the differential amplifier output is below the threshold which will turn the first 4049 gate from binary low to high. As an exercise, I determined the minimal DC bias voltage required for the first Figure 5 gate. Reliable triggering was obtained with a bias as low as 4.40 volts using a 4K7/2K7 voltage divider. It is easier to just use the VCC/2 rule as shown.
I encourage you to perform these little sidebar experiments. Write them in your QRP notebook for future reference.
Note the load resistor is now 220 ohms. At this point, I showed my work to Wes, W7ZOI and he suggested using a 220 ohm resistive load when terminating 4000 series logic stages. Changing the load from 51 to 200 ohms did not change the waveform shape or symmetry much, but it nearly tripled the AC output voltage.

The VFO final signal stage is normally DC-coupled to your switch product detector. That is; normally, you do not use an output blocking capacitor. For a consistent web page presentation from start to finish, the final stage load resistors are AC-coupled. Note that Figure 8 is DC coupled and is from an actual receiver experiment.

Shown above is the VFO waveform at the output of the Figure 5 inverter stages. This further signal conditioning really cleaned up the VFO output. The combination of the differential amp followed by 1-2 inverter stages seems to be a good method to symmetrically square up a sine wave. If you require a VFO with a single, square wave output, this might be a circuit to consider.
In all cases, you must ensure the output AC voltage is appropriate for whatever device you are driving. You can vary the AC output voltage many different ways, including changing RX in Figure 1, changing the VCC, or perhaps increasing or decreasing the value of the interstage coupling capacitors.

Shown above on top is the "unbalanced" output waveform of Figure 6. This circuit actually ruined the symmetry of the AC waveform, plus each output is quite different. Observe the differences between A and B on the top "unbalanced" photo. There are techniques available to better balance the output waveform in such a circuit. For an example, please refer to  Figure 6 on this web page by Sergio, IK4AUY. He uses a 74HC86N XOR chip to drive a switch. I built a popcorn version of his balancer (Figure 7) and the output of this circuit is shown as the "balanced" A and B on the bottom half of the photo.

Shown above in Figure 7 is the schematic for my "popcorn" XOR output balancer.  Balancing for me was to adjust the 10K pot until the waveforms looked about the same in the scope when looking straight on. The DC voltage on the wiper of the 10K pot when A and B appeared to be balanced was 5.09v. Further experimentation was conducted and one outcome appears as Figure 8.

Shown above in Figure 8 is a popcorn XOR balancer schematic used in an experimental receiver. I used a VCC/2 bias and was pleased with the output waveform balance. The loads are DC-coupled 51 ohm resistors. The DC voltage at pins 10 and 11 was not high enough to directly drive logic and this was disappointing.

Shown above is the Figure 8 breadboard. Temporary 51 ohm load resistors are connected to pins 10 and 11 so the output could be examined with an oscilloscope.

Shown above is the Figure 8 experiment output waveform.

Shown above in Figure 9 is a 4013 configured as a divide by 2.

Shown above is the output waveform of the Figure 9 circuit. The rise and fall times are sharper than ever. What an outstanding circuit! It may be worthwhile to consider doubling the VFO frequency in your project, just so you can use a flip-flop. Frequency doublers are easy to make and example circuits and great discussion may be found in EMRFD. In addition, EMRFD Figure 6.91 has some more great ideas for driving a FET bus switch mixer or product detector.

Shown above in Figure 10 is a practical implementation using a D-flip flop driven by a BJT driver. For more information on this transistor stage click here for the supplemental page.
I have been advised to use the 74HC series instead of the 4000 series of digital logic ICs for working at HF. For a D flip-flop, this is the 74HC74 and for a XOR chip, this is the 74HC86N. They cost the same or less than their 4000 series versions and must be run at ~ 5 volts. In addition, most of the lower resistance switches are also 5 volt parts and so it makes sense to use the 74HC parts. The Figure 1 VFO was doubled to 14 MHz with a measured output of -0.46 dBm (0.6 volts peak to peak into 50 ohms) to switch Figure 10. The output was of course, 7 MHz. Waveform balance with a flip-flop is excellent.

Shown above is the 7 MHz output waveform of the Figure 10 circuit. My waveforms look better than they really are as my old Tektronix oscilloscope bandwidth is only 15 MHz. The rise/fall times also would be faster on a high bandwidth scope.

Shown above in Figure 11 is the frequency multiplier used to double the Figure 1 VFO for driving Figure 10. The entire Q2 buffer of Figure 1 was replaced with this circuit.

The experimenter must decide what he or she wants to do, and which path to take. This really is a journey. So many circuits, so many ideas; which to choose?  Regards!