Supplement to the VFO 2009 Web Page
This web page is a supplement to the VFO 2009 Web Page
Figure 10 Bipolar Transistor Notes
This circuit is from EMRFD and is an analog to digital interface for the VFO. I did not understand the circuit, so I asked Wes, W7ZOI to explain his design criteria and
the basic circuit function. This transistor circuit is a driver.
The purpose of this transistor driver is to positive edge trigger a D flip-flop. The paramount criterion was that the transistor collector has a quiescent bias voltage that was between the minimal acceptable logic high and logic low DC voltages on the 74HC74 clock input. See this
chart for details about this topic.
The correct DC collector voltage is set via feedback from a voltage divider (in
this case, a 10K and 4K7 resistor). The collector voltage (shown above in Figure
1A) was measured at 2.36 VDC, which is perfect as it is between the logic low
and high state of the 74HC device which it drives.
This transistor circuit is also a high gain amplifier, however, its primary function is that of a driver. Refer to figure
1B. When connected to the VFO output, the base voltage drops to 0.30 volts. This is an average DC voltage
because it fluctuates
as the AC waveform swings up and down. More or less AC drive on the input will change this
DC voltage.
When connected to the VFO output, the collector voltage dropped
to 0.71 VDC. Again, this is an average, as when the AC swings positive, the the
collector voltage will drop down to saturation (where collector voltage is
less than base voltage) and then increase towards the positive supply. It does
not have to go into cutoff; just to 3.2 volts or so. It also does not have to go
into saturation; just to below the 1.3 volts or so. Thus, the transistor remains
between cutoff and saturation when appropriately driven with a sine wave.
Our VFO serves as the clock and data on the D flip-flop inputs are only
transferred to the flip-flop's outputs on the positive edge of a clock pulse.
Positive edge triggering means that the output only responds to the input
changes when the clock signal transitions from logic low to logic high. It is interesting to
view
the transistor base and collector waveforms in the oscilloscope. What a fantastic little
circuit! You can find additional information and some practical examples in EMRFD. My
special thanks to Wes, W7ZOI for helping me to better understand his design.
Positive Edge Triggering
The triggering of a positive edge triggered flip flop is better understood viewing a graphic like above. The instant the waveform goes positive, the flip flop is triggered. It is easy to understand why a square wave is desirable for clean triggering.
